1. Field of the Invention
This invention relates to a semiconductor memory of the type called layer-built CMOS type SRAM.
2. Description of the Prior Art
A complete CMOS type SRAM includes a large number of memory cells each of which has such a construction as shown FIG. 2. Referring to FIG. 2, the memory cell is composed of a flip-flop composed of a pair of N-channel MOS transistors 11 and 12 for driving and a pair of P-channel MOS transistors 13 and 14 for a load, and a pair of N-channel MOS transistors 15 and 16 for transfer.
A grounding line 21 is connected to source regions of the N-channel MOS transistors 11 and 13 while power source lines 22 and 23 are connected to source regions of the P-channel MOS transistors 13 and 14, respectively. Meanwhile, a word line 24 serves as gate electrodes of the N-channel MOS transistors 15 and 16, and bit lines 25 and 26 are connected to either ones of source/drain regions of the N-channel MOS transistors 15 and 16, respectively.
As a type of such complete CMOS type SRAM, there is a layer-built CMOS type SRAM wherein the P-channel MOS transistors 13 and 14 are each formed from a thin film transistor and the thin film transistors are layered on the N-channel MOS transistors 11 and 12.
FIG. 3 shows such P-channel MOS transistors 13 and 14 in a layer-built CMOS type SRAM which is disclosed in Japanese Patent Application No. 1-91519 filed by the applicant of the present application.
In the layer-built CMOS type SRAM, gate electrodes of the P-channel MOS transistors 13 and 14 are formed from polycrystal Si films 31 and 32 in an upper layer on the N-channel MOS transistors 11 and 12, and active regions of and the power source lines 22 and 23 for the P-channel MOS transistors 13 and 14 are formed from polycrystal Si films 33 and 34 in a further upper layer.
Accordingly, an overlapping portion of the polycrystal Si film 33 with the polycrystal Si film 31 forms a channel region of the P-channel MOS transistor 13 while an overlapping portion of the polycrystal film 34 with the polycrystal Si film 32 forms a channel region of the P-channel MOS transistor 14.
It is to be noted that drain regions of the P-channel MOS transistors 13 and 14 of the polycrystal Si films 33 and 34 are connected to the polycrystal Si films 32 and 31 by way of contact holes 33a and 34a, respectively.
In the layer-built CMOS type SRAM described above, however, each of the channel regions of the P-channel MOS transistors 13 and 14 have a linear profile. Consequently, where the area of the memory cell is maintained, the channel length of the P-channel MOS transistors 13 and 14 cannot be made longer than the that of the present memory cell.
Accordingly, with the layer-built CMOS type SRAM described above, it is difficult to decrease leak currents, that is, currents upon waiting, of the P-channel MOS transistors 13 and 14 to obtain a high data holding characteristic.